The present invention relates to multi-queue storage devices generally and, more particularly, to a method and/or architecture of width and depth expansion in a high speed multi queue system.
Referring to FIG. 1 a block diagram of a conventional circuit 10 for width expansion of a first-in first-out (FIFO) device is shown. The circuit 10 comprises a FIFO 12, a FIFO 14, a bus WDATA[79:0] and a bus RDATA[79:0]. The 80-bit bus WDATA[79:0] writes data to the FIFOs 12 and 14 through a 40-bit bus [39:0] and a 40-bit bus [79:40]. The 80-bit bus RDATA[79:0] reads the data from the FIFOs 12 and 14 through a 40-bit bus [39:0] and a 40-bit bus [79:40]. The FIFOS 12 and 14 each communicate through the 40-bit data busses [39:0] and [79:0] creating an 80-bit width circuit 10. The bus WDATA[79:0] and the bus RDATA[79:0] create point-to-point connections between (i) the FIFOs 12 and 14 and (ii) various reading and writing devices (not shown).
A write clock signal WCLK is presented to an input 16 of the FIFO 12 and to an input 18 of the FIFO 14. A write enable signal WEN is presented to an input 20 of the FIFO 12 and to an input 22 of the FIFO 14. A read clock signal RCLK is presented to an input 24 of the FIFO 12 and to an input 26 of the FIFO 14. A read enable signal REN is presented to an input 28 of the FIFO 12 and to an input 30 of the FIFO 14. Data is written to the FIFO 12 and/or 14 on a rising edge of the clock signal WRLK when the enable signal WEN is active (or asserted). The data is read from the FIFO 12 and/or 14 on a rising edge of a read clock signal RCLK when the read enable signal REN is active.
The circuit 10 additionally comprises a full flag logic block 29 and an empty flag logic block 31. The full flag logic block 29 generates full flags in response to the fullness of the FIFOs 12 and 14. An output 34 of the FIFO 12 is connected to an input 32 of the full flag logic block 29. An output 38 of the FIFO 14 is connected to an input 36 of the full flag logic block 29. The empty flag logic block 31 generates empty flags in response to the emptiness of the FIFOs 12 and 14. An output 42 of the FIFO 12 is connected to an input 40 of the empty flag logic block 31. An output 46 of the FIFO 14 is connected to an input 44 of the empty flag logic block 31. Logic flags for the circuit 10 are generated in response to the emptiness/fullness of the FIFOs 12 and 14.
The circuit 10 cannot deal with multi-queue configuration, status information, queue selection, queue reset operation and/or multicast/broadcast support functions. As the spread (i.e., the number of FIFOs) of the circuit 10 increases, the write enable signal WEN and the read enable signal REN require point-to-multipoint additional circuitry to avoid bus contention at the read interface.
Referring to FIG. 2 a block diagram of a conventional circuit 50 for depth expansion of FIFOs is shown. The circuit 50 comprises a FIFO 52, a FIFO 54, a bus WDATA[39:0] and a bus RDATA[39:0]. The 40-bit bus WDATA[39:0] is connected to an input 56 of the FIFO 52 and to an input 58 of the FIFO 54. The 40-bit bus RDATA[39:0] is connected to an output 60 of the FIFO 52 and an output 62 of the FIFO 54. The 40-bit bus WDATA[39:0] and the 40-bit bus RDATA[39:0] are each connected in parallel with the FIFOs 52 and 54. The parallel buses WDATA[39:0] and RDATA[39:0] create a FIFO having twice the depth of either the FIFO 52 or 54.
Data is written into the FIFO 52 and/or 54 through the bus WDATA[39:0]. The data is read from the FIFO 52 and/or 54 through the bus RDATA[39:0]. The busses WDATA[39:0] and RDATA[39:0] are point-to-multipoint connections between (i) the FIFOs 52 and 54 and (ii) various reading and writing devices (not shown).
A write clock signal WCLK is presented to an input 64 of the FIFO 52 and to an input 66 of the FIFO 54. A write enable signal WEN is presented to an input 68 of the FIFO 52 and an input 70 of the FIFO 54. A read clock signal RCLK is presented to an input 72 of the FIFO 52 and to an input 74 of the FIFO 54. A read enable signal REN is presented to an input 76 of the FIFO 52 and an input 78 of the FIFO 54. Data is written to the FIFO 52 and/or 54 on a rising edge of the clock signal WRLK when the enable signal WEN is active. The data is read from the FIFO 52 and/or 54 on a rising edge of a read clock signal RCLK when the read enable signal REN is active.
The circuit 50 additionally comprises a full flag logic block 80 and an empty flag logic block 81. The full flag logic block 80 generates full flags in response to the fullness of the FIFOs 52 and 54. An output 83 of the FIFO 52 is connected to an input 82 of the full flag logic block 80. An output 85 of the FIFO 54 is connected to an input 84 of the full flag logic block 80. The empty flag logic block 81 generates empty flags in response to the emptiness of the FIFOs 52 and 54. An output 87 of the FIFO 52 is connected to an input 86 of the empty flag logic block 81. An output 89 of the FIFO 54 is connected to an input 88 of the empty flag logic block 81. Logic flags for the circuit 50 are generated in response to the emptiness/fullness of the FIFOs 52 and 54.
The circuit 50 requires additional circuitry for depth expansion. The FIFOs 52 and 54 are connected in a daisy chain type configuration. A write token pin WTI 90 of the FIFO 54 is connected to a write token pin WTO 91 of the FIFO 52. A read token pin RTI 92 of the FIFO 54 is connected to a read token pin WTO 93 of the FIFO 52. A write token pin WTO 95 of the FIFO 54 is connected to a write token pin WTI 94 of the FIFO 52. A read token pin WTO 97 of the FIFO 54 is connected to a read token pin RTI 96 of the FIFO 52. The write token pins WTI 90, WTO 91, WTI 94 and WTO 95 are used to implement write depth expansion. The read token pins RTI 92, RTO 93, RTI 96 and RTO 97 are used to implement read depth expansion.
The FIFO 52 passes a write token to the pin WTI 90 during a full condition. The write token forces a next data packet to be written in the FIFO 54. The FIFO 54 passes the write token back to the pin 94 of the FIFO 52 during a full condition. In a case where both the FIFOs 52 and 54 are full, the full flag logic block 80 will assert a full flag. The read tokens of the FIFOs 52 and 54 operate similarity to the write tokens and are passed between the two FIFOs 52 and 54.
The circuit 50 cannot implement a delayed queue select write operation. The delay queue select write operation cannot be implemented because each of the FIFOs 52 and 54 need to know a queue address before determining whether the write token is present. In order for delayed queue selection write operation to be implemented, the FIFOs 52 and/or 54 need to store data from the start-of-packet.
The delay queue selection write operation requires a point-to-multipoint data interface. The point-to-multipoint interface requires additional circuitry and in some cases, may even be impossible as the frequency of operation increases. The management interface further requires additional circuitry and in some cases, may even be impossible as the frequency of operation increases.
The delay queue select operation requires additional external logic to determine the flag status of each queue that is presented on the pin. For example, if 16 flags are presented on the pins for full and empty flags simultaneously, 32 external flag detection logic circuits would be required. The delay queue select further requires complicated end of packet (EOP) logic communication between chips. Additionally, the delay queue selection operation requires logic to avoid bus contention at the read interface.
The present invention concerns an apparatus configured to read and write data in a plurality of memories. The plurality of memories may be configured to store and present the data in response to (i) a write data path and (ii) a read data path. One of the plurality of memories may be configured to control the remainder of the plurality of memories in response to one or more write signals and (ii) one or more read signals.
The objects, features and advantages of the present invention include providing a circuit for multi-queue storage that may implement (i) a width expansion scheme allowing multi-queue configuration, status information, queue selection, queue reset operation and multicast/broadcast support functions, (ii) high speed point-to-multipoint connections, (iii) a delayed queue select write operation, (iv) point-to-multipoint data interfaces that may not have a need for additional circuitry, (v) a flag status scheme that may not require external logic to determine the flag status of each queue that is presented on the pin, (vi) communication between chips that may not require complicated end of packet logic and/or (vii) a read interface that may not require additional logic to avoid bus contention at the read interface.